Pixel clock spread spectrum modulation

ABSTRACT

Circuits, methods, and apparatus that reduce the peak or maximum EMI generated by video signals provided to a CRT or digital display monitor. One exemplary embodiment provides for spreading the spectrum of the video signal in order to spread or diffuse its peak spectral component. This may be done by spreading the spectrum of a pixel clock that is used to clock or time pixel information provided to the monitor. One embodiment spreads the spectrum of the pixel clock by varying the frequency of its operation. The pixel clock is generated by a phase-locked loop having a number of dividers. These dividers divide the frequency of one or more of the signals around the phase-locked loop. The divide ratio is varied as a function of time, resulting in a variation of an output signal frequency as a function of time.

BACKGROUND

The present invention relates to reducing electromagnetic interference(EMI) generated by computer systems generally, and more particularly toreducing EMI by spreading the emission spectrum of pixel clock signalsand pixel information provided to CRTs and digital displays.

Electronic equipment sold in the United States typically must meetcertain regulations regarding the emission of electromagneticinterference. These and other regulations are generated by the FederalCommunication Commission. They help equipment to be used in proximitywith other equipment without impairing the other equipment's operation.Other regulatory bodies, such as the European Union have similarrequirements. The requirements of these regulations are beyond the scopeof this document.

If these emission standards are not met by an initial design of anelectronic equipment product, several costs are incurred. For example,the product may be delayed, resulting in lost opportunity costs. Also,corrective action may need to be taken, such as the incorporation ofmore complicated and expensive components and shielding. Further testingis likely to be required to ensure compliance, with its associated costsand delays.

EMI is caused by signals being transferred around electronic systems,particularly from one electronic component in the system to another.Generally, the stronger a signal component at a particular frequency,the higher the EMI at that frequency. The peak EMI spectral component istypically of most concern and the component that needs to be reduced toachieve compliance.

One type of electronic equipment that receives much attention from anEMI point of view are monitors such as cathode-ray tube monitors (CRTs)and digital displays, such as flat panel monitors. In particular, thesignals that drive these monitors, video signals, create EMI that maycause compliance difficulties.

Conventional solutions to this problem include the use of filters orchokes that reduce the edge rate of the video signal. Adding shieldingmay make further improvements. But these add costs and can degrade imagequality.

Thus, what is needed are circuits, methods, and apparatus that provide areduction in the maximum EMI generated by video signals without addingcostly devices or shielding, and without degrading image qualitynoticeably.

SUMMARY

Accordingly, embodiments of the present invention provide circuits,methods, and apparatus that reduce the peak or maximum EMI generated byvideo signals provided to a CRT or digital display monitor. Oneexemplary embodiment provides for spreading the spectrum of the videosignal in order to spread or diffuse its peak spectral component. Invarious embodiments, this is done by spreading the spectrum of a pixelclock that is used to clock or time pixel information provided to themonitor.

One exemplary embodiment spreads the spectrum of the pixel clock byvarying the frequency of its operation. This particular embodimentgenerates its pixel clock using phase-locked loop having a number ofdividers. These dividers divide the frequency of one or more of thesignals around the phase-locked loop. The divide ratio is varied as afunction of time, resulting in a variation of an output signal frequencyas a function of time. The output signal may then be used as the pixelclock, or the pixel clock may be derived from this signal. Embodimentsof the present invention may incorporate one or more of these and thevarious features described herein.

Another exemplary embodiment of the present invention provides anintegrated circuit. This integrated circuit includes a phase-locked loophaving a divider and is configured to provide a pixel clock having avariable frequency. The integrated circuit also includes an output logiccircuit configured to receive the pixel clock and further configured toprovide pixel information clocked by the pixel clock. The divider isconfigured to divide a signal by a value, and this value is variableover time.

A further exemplary embodiment of the present invention provides amethod of providing a video signal. This method includes generating aclock signal having a frequency, receiving a synchronizing signal,varying the clock frequency at a rate synchronous with the synchronizingsignal, and providing a plurality of pixels at the clock frequency.

Another exemplary embodiment of the present invention provides anintegrated circuit. This integrated circuit includes a clock generatingcircuit configured to provide a clock signal having a variablefrequency, an output circuit configured to receive pixel information andprovide the pixel information timed to the clock signal, and adigital-to-analog converter configured to receive the pixel informationtimed to the clock signal and further configured to provide an analogsignal to a monitor.

A better understanding of the nature and advantages of the presentinvention may be gained with reference to the following detaileddescription and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an improved computer system 100 thatbenefits by the incorporation of embodiments of the present invention;

FIG. 2 illustrates a comparison between electromagnetic spectrumsproduced by a computer display driven in a conventional manner and acomputer display driven in accordance with an embodiment of the presentinvention;

FIG. 3 illustrates a problem that occurs when a pixel clock frequency ischanged over time;

FIG. 4A illustrates a horizontal synchronizing and a pixel clockmodulation signal for one embodiment of the present invention, whileFIG. 4B illustrates a horizontal synchronizing and a pixel clockmodulation signal for another embodiment of the present invention;

FIG. 5A illustrates the improvement in an electromagnetic spectrumproduced by a computer display driven in accordance with one embodimentof the present invention over a computer display driven in aconventional manner, while FIG. 5B illustrates the improvement in anelectromagnetic spectrum produced by a computer display driven inaccordance with another embodiment of the present invention over acomputer display driven in a conventional manner;

FIG. 6 illustrates a phase-locked loop and associated look-up tableaccording to an embodiment of the present invention; and

FIG. 7 is a block diagram of a portion of a graphics processor pipelinethat provides pixel information that has been retimed to a variablepixel clock.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1 is a block diagram of an improved computer system 100 thatbenefits by the incorporation of embodiments of the present invention.The improved computer system 100 includes an NVIDIA nForce™2 integratedgraphics processor (IGP) 110, an nForce2 media communications processor(MCP2) 120, memory 112 and 114, CPU 116, optional graphics processor 118and frame buffer 140, monitor 122, scanner or camera 134, mouse,keyboard, and printer 136, hard drives 138, soft modem 142, Ethernetnetwork or LAN 146, and audio system 148.

This revolutionary system architecture has been designed around adistributed processing platform, which frees up the CPU to perform tasksbest suited to it. Specifically, the nForce2 IGP 110 includes a graphicsprocessing unit (GPU) (not shown) which is able to perform graphicscomputations previously left to the CPU 116. Alternately, the nForce2IGP 110 may interface to an optional GPU 118 which performs thesecomputations. Also, nForce2 MCP2 120 includes an audio processing unit(APU), which is capable of performing many of the audio computationspreviously done by the CPU 116. In this way, the CPU is free to performits tasks more efficiently. Also, by incorporating a suite of networkingand communications technologies such as USB and Ethernet, the nForce2MCP2 120 is able to perform much of the communication tasks that werepreviously the responsibility of the CPU 116.

In this architecture, the nForce2 IGP 110 communicates with memories 112and 114 over buses 113 and 115. The nForce2 IGP 110 also interfaces toan optional graphics processor 118 over an advanced AGP bus 117. Invarious computer systems, optional processor 118 may be removed, and themonitor 122 may be driven by the nForce2 IGP 110 directly. In othersystems, there may be more than one monitor 122, some or all of whichare coupled to optional graphics processor 118 or the nForce2 IGP 110directly. The nForce2 IGP 110 communicates with the nForce2 MCP2 120over a HyperTransport™ link 121. The optional graphics processor 118 mayalso interface with external memory, which is not shown in this example.

The nForce2 MCP2 120 contains controllers for Ethernet connections 146and a soft modem 142. The nForce2 MCP 120 also includes interfaces for amouse, keyboard, and printer 136, and USB ports for cameras and scanners134 and hard drives 138.

This arrangement allows the CPU 116, the nForce2 IGP 110, and thenForce2 MCP2 120, to perform processing independently, concurrently, andin a parallel fashion.

Embodiments of the present invention may be used to reduce theelectromagnetic emission caused by signals provided by the nForce2 IGP110 or the processor 118 to the monitor 120. Conventionally thisreduction has been limited by the use of expensive filters, chokes,shielding, or combinations of these. Embodiments of the presentinvention reduce EMI in a way that allows lower cost filters or chokesto be used, the amount and complexity of shielding to be reduced, or acombination of these.

When the monitor 120 is a cathode-ray tube (CRT) type monitor, thenForce2 IGP 110 or processor 118 provides analog waveforms that controlthe amount of energy provided to three electronic guns. These electronguns produce streams of electrons that strike the monitor 120 screenilluminating its pixels. Variations in the analog waveforms as afunction of time produce variations in pixel illumination, resulting ina displayed image.

When each pixel is illuminated for the same period of time, thefrequency spectrums of the analog waveforms have a large component atthe frequency that is the reciprocal of this period. Similarly, if themonitor 120 is a flat-panel, plasma, or other digital monitor, the innForce2 IGP 110 or processor 118 provides a number of digital waveformsthat control the illumination of each pixel. Again, if each pixel isupdated at a constant rate, the frequency spectrums of these digitalwaveforms include large components at the frequency that is thereciprocal of this rate. In these or similar situations, these largefrequency components result in electromagnetic radiation at thatfrequency.

Electronic equipment sold in the United States typically must meetcertain federal communication commission (FCC) standards. Thesestandards typically limit the amount of electromagnetic interference(EMI) that electronic equipment may produce. Failure to meet thestandards often results in delays in bringing products to market.Additionally, there may be extra costs associated with more expensiveshielding, filtering, and further testing needed to bring the deviceinto compliance.

Again, for these reasons, it is desirable to reduce the EMI produced atany single frequency. One way to do this is to an employ spreading thespread spectrum techniques to the signals provided to the monitor 120.

FIG. 2 illustrates a comparison between electromagnetic spectrumsproduced by a computer display driven in a conventional manner and acomputer display driven in accordance with an embodiment of the presentinvention. This figure, as with the other included figures, is shown forillustrative purposes only, and does not limit either the possibleembodiments of the present invention or the claims.

The amplitude, or signal power, of the signals are plotted on Y-axis 204as a function of frequency along x-axis 202. The spectrums resultingfrom conventional signaling is greatly simplified as 210. In practicalsystems, there are many other frequency components present. For example,there are components at the harmonics of this frequency, and componentswhose location depends on the actual image being displayed. However, oneof the largest components may often be at the frequency that is thereciprocal of one-half the rate at which each pixel is updated by anelectron beam produced in a cathode-ray tube or by a digital signal in aflat-panel display, or by these and or other types of signaling on theseor other types of monitors. (The one-half term comes about because twopixels are needed for one “cycle” of intensity change.)

In general, the more the variation in intensity between pixels, thehigher the amplitude of the resulting emission frequency components.

Spectrum 220 illustrates the resulting spectrum if the update time foreach pixel is varied. As might be expected, the more the frequency isvaried, the more the amplitude of 220 is reduced and the more its widthis increased. In this way, by spreading the electromagnetic power, theworst-case amplitude is reduced, and therefore the worst-caseelectromagnetic interference is reduced.

Typically, the signals provided by an nForce2 IGP 110 or processor 118to the monitor 120 are clocked or timed by a clock signal referred to asa pixel clock. Accordingly, embodiments of the present invention providecircuits, methods, and systems for spreading the spectrum of the pixelclock and thus the resulting electromagnetic interference pattern. Byspreading the spectrum of the pixel clock, the update time for eachpixel is varied.

FIG. 3 illustrates a problem that occurs as a pixel clock frequency ischanged in order to vary the update time for each pixel. This figureincludes a monitor screen 310 and a single pixel 320 for illustrativepurposes.

In a typical monitor, the screen 310 includes a number of horizontallines (not shown). The pixels on each line are updated sequentially, andwhen one horizontal line is complete, the next one is begun. After eachline on the screen has been updated, the entire process begins again.The time it takes to update one line is the horizontal line rate, whilethe time to complete the screen is referred to as the first refreshrate.

Accordingly, each pixel 320 is updated or refreshed for an amount oftime that may vary over time. For example, during one screen refresh,the pixel may be updated for an amount of time corresponding to pixelsize 320. During the next screen refresh, the pixel may be updated foran amount of time shown as dashed line 330, which is an amount of time340 longer than its update time during the previous screen refresh. Ifthis variation of pixel width occurs on a CRT, the image appears toswim.

One solution used by embodiments of the present invention is tosynchronize the variation in the pixel clock or pixel update period tothe horizontal line rate. In that way, each individual pixel does notchange width from one screen refresh to another, rather different pixelsalong each horizontal line have slight variations in their width. In oneembodiment, the pixel width variation is the same for each horizontalline retrace. In this case, one column of pixels has a different widthfrom other columns of pixels. In other embodiments, pixel widths vary ina different manner each horizontal retrace. It should be noted that evena slight variation in pixel width leads to the very good EMI reductionwithout creating visible artifacts.

The horizontal retrace of a typical monitor is controlled by ahorizontal synchronizing signal, a referred to as HSYNC. Accordingly,various embodiments of the present invention synchronize the modulationor variation in frequency of the pixel clock and resulting image data tothe horizontal synchronizing signal. In other embodiments of the presentinvention, this modulation may be synchronized to other signals, such asthe in vertical synchronizing signal, typically referred to as VSYNC.

FIG. 4A illustrates a horizontal synchronizing and a pixel clockmodulation signal for one embodiment of the present invention. Ahorizontal synchronizing signal is plotted along a Y-axis of amplitude404 as a function of time on X-axis 402. HSYNC 410 includes an activetime period 412 during which each of the pixels on an individualhorizontal line are updated, and an inactive period 414, which may bereferred to as a blanking period during which a horizontal retraceoccurs and no pixels are updated.

The frequency of the pixel clock, or really the pixel clock modulationsignal, is plotted on Y-axis 406 in frequency as a function of time onX-axis 402. During the blanking time 414, the pixel clock may either bevaried, as indicated by lines 428, left constant as indicated by lines426, or allowed to drift or go to some other value. During thehorizontal retrace time 412, the pixel clock frequency may be varied asindicated by line segments 422 and 424. In this particular embodiment,the pixel clock frequency first increases then decreases, each forone-half of the horizontal retrace time, and each at a constant rate. Inother embodiments of the present invention, the pixel clock frequencymay increase or decrease a different number of times, at different orvarying rates, and the pixel clock frequency may be increased ordecreased in different orders.

As can be seen, in this particular embodiment, both the beginning andend of each pixel clock modulation cycle is synchronized to thebeginning and end of the HSYNC active period 412. This ensures that thepixel clock is at each of the frequencies in its range for the sameamount of time. It will be appreciated by one skilled in the art thatthere are many other waveforms that are synchronized to the beginningand end of an HSYNC active period and that may be used as the pixelclock modulation signal. Also, different waveforms may be used duringdifferent horizontal retrace periods, though the same waveform shouldgenerally be used from one screen refresh to another to avoid having theimage “swim,” though an exception may be made if the contents of theimage is updated or changed significantly.

FIG. 4B illustrates a horizontal synchronizing and a pixel clockmodulation signal for another embodiment of the present invention.Again, a horizontal synchronizing signal 430 is plotted along a Y-axis405 as a function of time on X-axis 403. Also, the pixel clock frequencyis plotted along Y-axis 407 as a function of time along X-axis 403.

In this particular embodiment, during the active period 432, the pixelclock frequency increases as is indicated by line segments 442. At somepoint, the pixel clock frequency begins to decrease until the end of theactive period 432.

As can be seen, in this embodiment, the end of the pixel clockmodulation signal 440 is not synchronized to the HSYNC signal 430. Thismeans that the pixel clock is at some frequencies for a longer period oftime than it is at other frequencies. The spectral ramifications of thisare shown below. It will be appreciated by one skilled in the art thatthere are many waveforms that may be used as the pixel clock modulationsignal 440, some of which may be synchronized to an HSYNC start time,others that are synchronized to other portions of an HSYNC or HSYNCrelated signal. Further, a different waveform may be used for differenthorizontal retraces, though the same waveform should be used for thesame line from one screen refresh to another to avoid having the image“swim” as described above.

FIG. 5A illustrates the improvement in an electromagnetic spectrumproduced by a computer display driven in accordance with an embodimentof the present invention, such as the embodiment of FIG. 4A, over acomputer display driven in a conventional manner. The spectrumamplitudes are plotted on Y-axis 504 as a function of frequency alongthe X-axis 502.

As before, in conventional systems the pixel clock does not change,resulting an EMI spectrum that may be simplified as 510. Embodiments ofthe present invention, such as the embodiment illustrated FIG. 4A,spread the pixel clock evenly over a frequency range resulting in thespectrum 520.

Again, these spectrum are highly simplified for illustrative purposes.Practical spectrums contain harmonics, sidebands, and other frequencyartifacts.

FIG. 5B illustrates the improvement in an electromagnetic spectrumproduced by a computer display driven in accordance with anotherembodiment of the present invention, such as the embodiment of FIG. 4B,over a computer display driven in a conventional manner. Again, thespectrum amplitudes are plotted along a Y-axis 505 as a function offrequency along an X-axis 503. Again, a conventional system produces thespectrum 530, whereas embodiments of the present invention such as theone illustrated in FIG. 4B results in the spectrum 540.

Again, the embodiment illustrated in FIG. 4B provides a pixel clockfrequency that is present at one frequency longer than anotherfrequency. Accordingly, the spectrum 540 has a high point 550, whichcorresponds to the pixel clock frequency having a higher occurrence. Inmost systems, this should not compromise EMI significantly, and may makethe design of the supporting circuitry simpler. One such supportingcircuit is shown as the next-figure.

FIG. 6 illustrates a phase-locked loop and associated look-up tableaccording to an embodiment of the present invention. This circuitincludes a phase-locked loop 610, and dividers 620, 630, and 640.

A horizontal synchronizing signal is received on line 625 by thedividers 620. The divider 620 divides the frequency of the HSYNC signalby a factor of M and provides an output on line 625 to the phase-lockedloop 610. The phase-locked loop 610 provides a clock signal on line 615,which is divided by a divider 640 and provided as the pixel clock online 645. The output of the phase-locked loop on line 615 is alsodivided by divider 630, which provides a divided phase-locked loopoutput on line 635 to the input of phase-locked loop 610. Thephase-locked loop 610 compares the phase and frequencies of the signalson line 625 and 635, and provides the proper clock output on line 615.

In this specific embodiment, the frequency of the HSYNC signal isdivided by divider 620 by a factor of M. Also, the signal provided bythe PLL 610 on line 615 is divided by the divider 640 by a factor of Pand by the divider 630 by a factor of N.

Accordingly, there are N/MP PCLKs for each HSYNC cycle on line 625.Thus, the frequency of the clock period may be varied by changing M, N,or P. A specific embodiment of the present invention utilizes a lookuptable 615 having a number of entries 652 for M, N, and P. These tableentries may be utilized for one or a number of clock periods. Each entryin the table may be varied, resulting in clock modulation signals suchas those shown in FIGS. 4A and 4B.

This table may be located in memory on the same integrated circuit asthe phase-locked loop, or in a frame buffer or system memory. The tablemay alternately be formed of registers or other storage devices. Inanother embodiment of the present invention, table 615 may be replacedby other tables and other entries, or by other signals, such as timevarying signals.

The pixel clock can then be used to clock or time pixel information,that is, the video signal. Typically this is done by an output circuit,such as a scanout engine or other logic circuit. A scanout engineretrieves pixel information from a memory, such as the frame buffer orgraphics memory 140 or system memory 112 in FIG. 1, and retimes it tothe pixel clock. The resulting output signal is then provided to amonitor, often after conversion to analog signals by digital-to-analogconverters. In other embodiments, the pixel clock is provided along withpixel information to a monitor. In either case, the video informationspectrum is spread, and the resulting maximum EMI is reduced.

In this particular embodiment, a digital PLL and lookup table is used.In other embodiments, analog circuitry may be used, and an analog signalmay be varied. For example, a bias voltage for a varactor diode or othercapacitance, or a voltage controlled oscillator control voltage may bemodulated, thus varying the pixel clock output. Further, if a digitalPLL is used, other circuitry, such as a counter, may be used in place ofa lookup table.

FIG. 7 is a block diagram of a portion of a graphics processor pipelinethat provides pixel information that has been retimed to a variablepixel clock. This circuitry includes a frame buffer or graphics memory710, frame buffer interface 720, scanout engine 730, phase-locked loop740, and digital to analog converters 750. Pixels are read out of theframe buffer 710 via the frame buffer interface at a memory clock rate.The phase-locked loop 740 may be the phase-locked loop of FIG. 6 orother phase-locked loop consistent with embodiments of the presentinvention.

The scanout engine 730 receives the pixel clock from the phase-lockedloop 740 and retimes the pixels to the pixel clock signal. The pixelsare converted to red, green, and blue analog signals by thedigital-to-analog converters 750 and provided to a monitor (not shown).It will be appreciated by one skilled in the art that other outputcircuits, for example circuits configured to drive digital displays, maybe made consistent with embodiments of the present invention.

The above description of exemplary embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit fhe invention to the precise formdescribed, and many modifications and variations are possible in lightof the teaching above. The embodiments were chosen and described inorder to best explain the principles of the invention and its practicalapplications to thereby enable others skilled in the art to best utilizethe invention in various embodiments and with various modifications asare suited to the particular use contemplated.

1. An integrated circuit comprising: a phase-locked loop having adivider and configured to provide a pixel clock having a variablefrequency; and an output logic circuit configured to receive the pixelclock and further configured to provide pixel information clocked by thepixel clock, wherein the divider is configured to divide a frequency ofa signal by a value, and wherein the value is variable over time, andwherein the value is determined by entries in a look-up table.
 2. Theintegrated circuit of claim 1 wherein the entries in the look-up tableare retrieved synchronously with a first signal.
 3. The integratedcircuit of claim 2 wherein the first signal is a horizontalsynchronizing signal.
 4. The integrated circuit of claim 3 wherein thepixel information is converted to an analog signal by adigital-to-analog converter after being retimed to the pixel clock. 5.The integrated circuit of claim 4 wherein the pixel informal ion isretrieved from a memory before being retimed to the pixel clock.
 6. Theintegrated circuit of claim 1 wherein the pixel clock frequency isvaried from a first frequency to a second frequency at a linear rate. 7.The integrated circuit of claim 1 wherein the pixel clock frequency isvaried from a first frequency to a second frequency at a non-linearrate.
 8. A method of providing a video signal, the method comprising:generating a clock signal having a frequency; receiving a synchronizingsignal; varying the clock frequency according to a waveform that issynchronous with a first edge of the synchronizing signal and notsynchronous with a second edge of the synchronizing signal such that theclock frequency at the first edge of the synchronizing signal isdifferent from the clock frequency at the second edge of thesynchronizing signal; and providing a plurality of pixels at the clockfrequency.
 9. The method of claim 8 wherein the synchronizing signal isa horizontal synchronizing signal.
 10. The method of claim 9 wherein theclock frequency is varied by varying an analog voltage.
 11. The methodof claim 9 wherein the clock signal is generated by a phase-locked loopincluding a divider.
 12. The method of claim 11 wherein the dividerdivides the frequency of an input signal by a value, and the valuevaries as a function of time.
 13. The method of claim 12 wherein thevalue is determined by entries in a look-up table.
 14. An integratedcircuit comprising: a clock generating circuit configured to provide aclock signal having a variable frequency, wherein the variable frequencyvaries in a pattern that repeats each cycle of a first signal, such thatthe variable frequency has a first value at a first edge of the firstsignal, a second value at a second edge of the first signal, and a thirdvalue at a time between the first edge of the first signal and thesecond edge of the first signal, the third value different than thefirst value, and the second value between the first value and the thirdvalue; an output circuit configured to receive pixel information andprovide the pixel information timed to the clock signal; and adigital-to-analog converter configured to receive the pixel informationtimed to the clock signal and further configured to provide an analogsignal to a monitor.
 15. The integrated circuit of claim 14 whereinclock generating circuit is a phase-locked loop having a divider, thedivider configured to divide a signal by a value, wherein the valuevaries as a function of time.
 16. The integrated circuit of claim 15wherein the value is determined by entries in a look-up table.
 17. Theintegrated circuit of claim 14 wherein the first signal is a horizontalsynchronizing signal.
 18. The integrated circuit of claim 17 wherein theclock signal frequency is varied from the first value to the third valueat a linear rate.
 19. The integrated circuit of claim 17 wherein theclock signal frequency is varied from a the first value to the thirdvalue at a non-linear rate.
 20. The integrated circuit of claim 2wherein the variable frequency varies in a pattern that repeats eachcycle of the first signal; such that the variable frequency has a firstvalue at a first edge of the first signal, a second value at a secondedge of the first signal, and a third value at a time between the firstedge of the first signal and the second edge of the first signal, thethird value different than the first value, and the second value betweenthe first value and the third value.
 21. The integrated circuit of claim20 wherein a resulting EMI spectrum for the pixel clock has a higherlevel in a frequency range between the third value and the second valuethan in a frequency range between the first value and the second value.22. The integrated circuit of claim 14 wherein a resulting EMI spectrumfor the clock signal has a higher level in a frequency range between thethird value and the second value than in a frequency range between thefirst value and the second value.